Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, and are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits.
On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through the bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding.
Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls. In a conventional interconnect structure used in the WLCSP, an aluminum pad is formed to electrically connect to devices formed on a surface of the silicon substrate in the same die. A passivation layer is formed. The passivation layer includes a portion over the aluminum pad. An opening is formed in the passivation layer to expose the aluminum pad. A first polymer layer is formed over the passivation layer, and is patterned to expose the aluminum pad. A post-passivation interconnect (PPI) line is then formed, followed by the formation of a second polymer layer, and an under-bump metallurgy (UBM). The UBM is formed in an opening penetrating through the second polymer. A solder ball may then be placed on the UBM. The first and the second polymers may be formed of spin coating. The thickness of the second polymer is typically between about 7 μm and about 10 μm.
The above-discussed WLCSP may be bonded onto a printed circuit board (PCB). To be able to have the option of replacing a defect WLCSP bonded on the PCB with a good WLCSP, it is preferable that no underfill is filled between the WLCSP and the PCB. Such configuration, however, limits the die size of the current WLCSP technology to 5 mm×5 mm and below. The reason is that without the protection of the underfill, the thermal mismatch between the die in the WLCSP and the PCB can induce solder joint crack during the thermal cycling or drop test. Therefore, for large-die applications, flip-chip packaging is required to use underfill, and direct-on-board die bonding is allowed.